I/F conversion device and photo-detection device

ABSTRACT

An I/F converter  10  includes a first comparator portion  11   1 , a second comparator portion  11   2 , a current mirror circuit  14 , a reference voltage source  15 , an SR-type flip-flop circuit  16 , a buffer amplifier  18 , a first capacitive element C 1 , a second capacitive element C 2 , a switch SW 1 , a switch SW 2 , a switch SW 11 , and a switch SW 21 . The respective operational characteristics of the first comparator portion  11   1  and the second comparator portion  11   2  are identical to each other. The respective capacitance values of the two capacitive elements C 1  and C 2  are equal to each other. The I/F converter  10  is connected at its input end  10   a  to a photodiode PD, such that a current generated in the photodiode PD is inputted to the input end  10   a , allowing a signal at a frequency corresponding to the amplitude of the inputted current to be outputted from the buffer amplifier  18  to the counter portion  19 . Accordingly, provided is an I/F converter and a photodetector which can realize a high input/output related linearity with high accuracy over a wide dynamic range.

TECHNICAL FIELD

The present invention relates to a current-to-frequency (I/F) converterwhich outputs a signal at a frequency corresponding to the amplitude ofa current inputted to the input end, and also relates to a photodetectorwhich includes such an I/F converter and a photosensitive element.

BACKGROUND ART

Photosensitive elements (e.g., photodiodes or photomultipliers) canoutput a current corresponding in amplitude to the intensity of incidentlight, thereby detecting the light intensity based on the current value.Such a photosensitive element has a good linearity between the intensityof incident light and the output current value over a wide dynamic rangeof the intensity of incident light. On the other hand, it is known thatthe dynamic range of the sensitivity of the human eye to the intensityof light is about six orders of magnitude.

In this context, an A/D converter for inputting the value of a currentoutputted from the photosensitive element for analog to digitalconversion is required to output a digital value of a number of bitscorresponding to the intensity of light over such a wide dynamic range.For example, corresponding to the dynamic range of light intensity beingsix orders of magnitude, the A/D converter is required to output adigital value of 20 bits. However, it is difficult to realize such anA/D converter that outputs a digital value of 20 bits.

To address such a problem, there has been suggested an I/F converterwhich outputs a signal at a frequency corresponding to the amplitude ofinputted current (e.g., see Japanese Patent Application Laid-Open No.2002-107428). This I/F converter inputs the value of a current outputtedfrom the photosensitive element to output a pulsed signal at a frequencycorresponding to the magnitude of the value of the current (i.e., theintensity of light made incident upon the photosensitive element).Accordingly, by counting the number of pulses per unit time in thesignal outputted from the I/F converter, it is possible to obtain thelight intensity as a digital value over a wide dynamic range.

FIG. 12 is a view illustrating the configuration of a conventional I/Fconverter disclosed in Japanese Patent Application Laid-Open No.2002-107428. An I/F converter 40 illustrated in this figure includes acurrent-to-voltage converting circuit 41, a transistor Tr1, a currentmirror circuits 42 and 43, a mirror integrator circuit 44, a comparatorcircuit 45, and a reference voltage source 46.

The current-to-voltage converting circuit 41, which has an operationalamplifier 41 a and a feedback resistive element Rf, inputs the currentvalue outputted from a current value detecting circuit 4 and thenconverts it into a voltage value corresponding to the current value tooutput the voltage value. The transistor Tr1 inputs, at its gateterminal, the voltage value outputted from the current-to-voltageconverting circuit 41, allowing the current of the value obtained bylogarithmically amplifying the voltage value to flow between the sourceterminal and the drain terminal. The current mirror circuit 42, whichhas transistors Tr2 and Tr3, amplifies the current outputted from thetransistor Tr1 for output. The current mirror circuit 43, which hastransistors Tr4 and Tr5, amplifies the current outputted from thecurrent mirror circuit 42 for output.

The mirror integrator circuit 44, which has an operational amplifier 44a and a feedback capacitive element C, inputs a current outputted fromthe current mirror circuit 43 to accumulate charges in the capacitiveelement C corresponding to the input current, and then outputs a voltagevalue corresponding to the amount of charges accumulated. The comparatorcircuit 45 compares amplitudes between the voltage value outputted fromthe mirror integrator circuit 44 and the reference voltage value V_(ref)outputted from the reference voltage source 46 to output a comparisonsignal indicating the result of the comparison. A switch 34 disposedbetween the input and output terminals of the operational amplifier 44 aof the mirror integrator circuit 44 inputs the comparison signal thathas been outputted from the comparator circuit 45 and passed through abuffer amplifier 33, thereby being opened or closed in accordance withthe comparison signal.

In the I/F converter 40, a current inputted to the mirror integratorcircuit 44 gradually increases the amount of charges accumulated in thecapacitive element C, thereby causing the value of the voltage outputtedfrom the mirror integrator circuit 44 to increase. Then after the valueof the voltage outputted from the mirror integrator circuit 44 exceedsthe reference voltage value V_(ref), the comparison signal outputtedfrom the comparator circuit 45 is inverted, thereby causing the switch34 to be closed and the capacitive element C to be discharged. When thecapacitive element C is discharged, the comparison signal is invertedagain and the switch 34 is opened, thus starting building up charges inthe capacitive element C. In this manner, charge and dischargeoperations repeatedly performed on the capacitive element C will causethe comparison signal outputted from the comparator circuit 45 to beturned into a signal that is representative of the repetition of thecharge and discharge operations and at a frequency corresponding to themagnitude of the value of the input current.

The I/F converter 40 includes the transistor Tr1 that has a logarithmicamplification characteristic. This is intended to improve the input andoutput related linearity between the input current value and the outputfrequency even when use of a transistor having no logarithmicamplification characteristic would cause such a high output frequency (alarge input current value) that cannot ensure a sufficient period oftime for discharging the capacitive element C. In other words, the I/Fconverter 40 is intended to improve the input and output relatedlinearity of the input current value over a wide dynamic range.

DISCLOSURE OF THE INVENTION

However, it is difficult for the conventional I/F converter to realize ahigh input and output related linearity between the input current valueand the output frequency with high accuracy over a wide dynamic range.Accordingly, it is also difficult for a photodetector incorporating suchan I/F converter and photosensitive element to realize a high input andoutput related linearity between the intensity of incident light and theoutput frequency with high accuracy over a wide dynamic range.

The present invention was developed to address the above-mentionedproblems. It is therefore an object of the present invention to providean I/F converter and a photodetector which can realize a high input andoutput related linearity with high accuracy over a wide dynamic range.

An I/F converter according to the present invention generates a signalat a frequency corresponding to an amplitude of a current inputted to aninput end, and the I/F converter comprises (1) switching means forselectively switching to either one of a first output end and a secondoutput end to output the current inputted to the input end, (2) a firstcapacitive element connected to the first output end of the switchingmeans to accumulate charge corresponding to inputted current, (3) firstdischarge means for discharging the charge accumulated in the firstcapacitive element, (4) a first comparator portion connected at itsinput terminal to one end of the first capacitive element to compareamplitudes between a voltage at the one end of the first capacitiveelement and a reference voltage, the first comparator portion outputtingfrom its output terminal a first comparison signal indicating a resultof the comparison, (5) a second capacitive element connected to thesecond output end of the switching means to accumulate chargecorresponding to inputted current, (6) second discharge means fordischarging the charge accumulated in the second capacitive element, and(7) a second comparator portion connected at its input terminal to oneend of the second capacitive element to compare amplitudes between avoltage at the one end of the second capacitive element and a referencevoltage, the second comparator portion outputting from its outputterminal a second comparison signal indicating a result of thecomparison.

When this I/F converter is set so that the switching means allows acurrent to be outputted to the first output end, the current inputted atthe input end flows into the first capacitive element via the switchingmeans, causing charges to be built in the first capacitive element. Asthe amount of charges accumulated in the first capacitive elementincreases, the voltage applied to the input terminal of the firstcomparator portion gradually increases and then grows greater than thereference voltage. Then, the first comparison signal outputted from theoutput terminal of the first comparator portion is inverted in level.The inversion in level of the first comparison signal will cause thecharges built in the first capacitive element to be discharged by thefirst discharge means, thereby allowing the first comparison signaloutputted from the output terminal of the first comparator portion to beinverted in level.

Thereafter, the setting is changed such that the switching means outputsthe current to the second output end, thereby allowing the currentinputted to the input end to flow into the second capacitive elementthrough the switching means to accumulate the charges in the secondcapacitive element. As the amount of charges accumulated in the secondcapacitive element increases, the voltage inputted to the input terminalof the second comparator portion gradually increases and then growsgreater than the reference voltage. Then, the second comparison signaloutputted from the output terminal of the second comparator portion isinverted in level. The inversion in level of the second comparisonsignal will cause the charges built in the second capacitive element tobe discharged by the second discharge means, thereby allowing the secondcomparison signal outputted from the output terminal of the secondcomparator portion to be inverted in level.

The operations repeated as described above cause the signals outputtedfrom the first comparator portion or the second comparator portion ofthe I/F converter to form a pulsed signal, the frequency of whichcorresponds to the amplitude of the current inputted to the input end.

To perform the above-mentioned operations, the I/F converter maypreferably further include timing control means to control the operationof each of the switching means, the first discharge means, and thesecond discharge means in accordance with the first comparison signaland the second comparison signal.

It is preferable that the I/F converter according to the presentinvention further includes (1) a third capacitive element connected atone end to the first output end of the switching means as well as to theinput terminal of the first comparator portion to accumulate chargecorresponding to inputted current, (2) third discharge means fordischarging the charge accumulated in the third capacitive element, (3)a fourth capacitive element connected at one end to the second outputend of the switching means as well as to the input terminal of thesecond comparator portion to accumulate charge corresponding to inputtedcurrent, (4) fourth discharge means for discharging the chargeaccumulated in the fourth capacitive element, (5) first connection meansfor selectively setting to either one of the states with the other endof the first capacitive element connected to a ground potential, withthe other end of the first capacitive element connected to the outputterminal of the first comparator portion, and with the other end of thefirst capacitive element opened, (6) second connection means forselectively setting to either one of the states with the other end ofthe second capacitive element connected to the ground potential, withthe other end of the second capacitive element connected to the outputterminal of the second comparator portion, and with the other end of thesecond capacitive element opened, (7) third connection means forselectively setting to either one of the states with the other end ofthe third capacitive element connected to the ground potential, with theother end of the third capacitive element connected to the outputterminal of the first comparator portion, and with the other end of thethird capacitive element opened, and (8) fourth connection means forselectively setting to either one of the states with the other end ofthe fourth capacitive element connected to the ground potential, withthe other end of the fourth capacitive element connected to the outputterminal of the second comparator portion, and with the other end of thefourth capacitive element opened. It is also preferable that each of thefirst comparator portion and the second comparator portion isselectively settable to either one of a comparator mode or an amplifiermode. Here, the comparator mode is a mode of operation for comparingamplitudes between the voltage inputted to the input terminal and thereference voltage to output a comparison signal indicating the result ofthe comparison from the output terminal. On the other hand, theamplifier mode is a mode of operation in which when the feedbackcapacitive element is connected between the input terminal and theoutput terminal, the voltage value corresponding to the amount ofcharges accumulated in the feedback capacitive element is outputted fromthe output terminal.

As is in this case, the third and fourth capacitive elements, thedischarge means for discharging the charges in each capacitive element,and the connection means for setting the connection state of eachcapacitive element may be further included in addition to the first andsecond capacitive elements, this arrangement allows for accumulatingcharges in the first capacitive element, the second capacitive element,the third capacitive element, and the fourth capacitive elementrepeatedly in that order. This in turn causes the signals outputted fromthe first comparator portion and the second comparator portion to form apulsed signal, the frequency of which corresponds to the amplitude ofthe current inputted to the input end.

In addition, to perform the above-mentioned operations, the I/Fconverter may preferably further include timing control means, thetiming control means provides control in accordance with the firstcomparison signal and the second comparison signal, and controls anoperation of each of the switching means, the first discharge means, thesecond discharge means, the third discharge means, the fourth dischargemeans, the first connection means, the second connection means, thethird connection means, the fourth connection means, the firstcomparator portion, and the second comparator portion.

The I/F converter according to the present invention may furtherpreferably include a reference voltage source for supplying thereference voltage to each of the first comparator portion and the secondcomparator portion, an SR-type flip-flop circuit for inputting the firstcomparison signal and the second comparison signal, a current mirrorcircuit for amplifying a current inputted to the input end for output tothe switching means, a first overvoltage protection circuit connected tothe input terminal of the first comparator portion to reset a potentialat the input terminal, and a second overvoltage protection circuitconnected to the input terminal of the second comparator portion toreset a potential at the input terminal.

A photodetector according to the present invention includes (1) aphotosensitive element for outputting a current of an amplitudecorresponding to an intensity of incident light, and (2) an I/Fconverter according to the present invention described above forinputting a current outputted from the photosensitive element togenerate a signal at a frequency corresponding to an amplitude of thecurrent. It is also preferable to further include a counter portion forcounting the number of pulses per unit time in the signal generated inthe I/F converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating the configuration of an I/F converter 10and a photodetector 1 according to a first embodiment;

FIG. 2 is an explanatory timing chart illustrating the operation of theI/F converter 10 according to the first embodiment;

FIG. 3 is a graph showing the operational characteristic of the I/Fconverter 10 and the photodetector 1 according to the first embodiment;

FIG. 4 is a view illustrating the configuration of an I/F converter 20and a photodetector 2 according to a second embodiment;

FIG. 5 is a view illustrating an exemplary circuit of each of a firstcomparator portion 21 ₁ and a second comparator portion 21 ₂;

FIG. 6 is a view illustrating an exemplary circuit of each of a firstovervoltage protection circuit 22 ₁ and a second overvoltage protectioncircuit 22 ₂;

FIG. 7 is an explanatory timing chart illustrating the operation of theI/F converter 20 according to the second embodiment;

FIGS. 8A to 8C are first explanatory views illustrating how each switchis opened or closed at each point in time and how each capacitiveelement is connected during operation of the I/F converter 20 accordingto the second embodiment;

FIGS. 9A to 9C are second explanatory views illustrating how each switchis opened or closed at each point in time and how each capacitiveelement is connected during operation of the I/F converter 20 accordingto the second embodiment;

FIGS. 10A to 10C are third explanatory views illustrating how eachswitch is opened or closed at each point in time and how each capacitiveelement is connected during operation of the I/F converter 20 accordingto the second embodiment;

FIGS. 11A and 11B are views illustrating the operational characteristicsof the I/F converter 10 of the first embodiment and those of the I/Fconverter 20 of the second embodiment for comparison purposes; and

FIG. 12 is a view illustrating the configuration of a conventional I/Fconverter.

BEST MODES FOR CARRYING OUT THE INVENTION

Now, the present invention will be explained below in more detail withreference to the accompanying drawings in accordance with theembodiments. Throughout the drawings, the same components are indicatedwith the same symbols and will not be explained repeatedly.

First Embodiment

First, a description will be made for an I/F converter and aphotodetector according to the first embodiment of the presentinvention. FIG. 1 is a view illustrating the configuration of an I/Fconverter 10 and a photodetector 1 according to the first embodiment.The photodetector 1 illustrated in this figure includes a photodiode PDfor outputting a current of an amplitude corresponding to the intensityof light made incident thereon, the I/F converter 10 for inputting acurrent outputted from the photodiode PD to generate a signal, and acounter portion 19 for counting the number of pulses per unit time inthe signal generated by the I/F converter 10.

The I/F converter 10 includes a first comparator portion 11 ₁, a secondcomparator portion 11 ₂, a current mirror circuit 14, a referencevoltage source 15, an SR-type flip-flop circuit 16, a buffer amplifier18, a first capacitive element C₁, a second capacitive element C₂, aswitch SW₁, a switch SW₂, a switch SW₁₁, and a switch SW₂₁.

The respective operational characteristics of the first comparatorportion 11 ₁ and the second comparator portion 11 ₂ are identical toeach other. The respective capacitance values of the two capacitiveelements C₁ and C₂ are equal to each other. The I/F converter 10 isconnected at its input end 10 a to the photodiode PD, such that acurrent generated in the photodiode PD is inputted to the input end 10a, allowing a signal at a frequency corresponding to the amplitude ofthe inputted current to be outputted from the buffer amplifier 18 to thecounter portion 19.

The current mirror circuit 14 amplifies the current inputted at theinput end 10 a for outputting to the switch SW₁ and the switch SW₂. Theswitch SW₁ is disposed between the output end of the current mirrorcircuit 14 and the inverting input terminal of the first comparatorportion 11 ₁. The switch SW₂ is disposed between the output end of thecurrent mirror circuit 14 and the inverting input terminal of the secondcomparator portion 11 ₂. The switch SW₁ and the switch SW₂ serve asswitching means for selectively switching to either one of a firstoutput end (a connection point to the inverting input terminal of thefirst comparator portion 11 ₁) and a second output end (a connectionpoint to the inverting input terminal of the second comparator portion11 ₂) to output the current inputted to the input end 10 a and havingpassed through the current mirror circuit 14.

The first capacitive element C₁ is connected at one end to the outputend of the current mirror circuit 14 via the switch SW₁ as well as tothe inverting input terminal of the first comparator portion 11 ₁. Theother end of the first capacitive element C₁ is connected to the ground.The first capacitive element C₁ can accumulate charges corresponding tothe current inputted. The switch SW₁₁ is disposed between the one end ofthe first capacitive element C₁ and the ground potential, serving asfirst discharge means for discharging the charges accumulated in thefirst capacitive element C₁.

The first comparator portion 11 ₁ inputs, at its inverting inputterminal, a voltage V₁ at the one end of the first capacitive elementC₁, and also inputs, at its non-inverting input terminal, a referencevoltage V_(ref) outputted from the reference voltage source 15, tocompare amplitudes between the voltage V₁ and the reference voltageV_(ref), and then outputs a first comparison signal S₁ indicating theresult of the comparison from the output terminal. The first comparisonsignal S₁ is at a high level when the voltage V₁ is less than thereference voltage V_(ref), while being at a low level when the voltageV₁ is greater than the reference voltage V_(ref).

The second capacitive element C₂ is connected at one end to the outputend of the current mirror circuit 14 via the switch SW₂ as well as tothe inverting input terminal of the second comparator portion 11 ₂. Theother end of the second capacitive element C₂ is connected to theground. The second capacitive element C₂ can accumulate chargescorresponding to the current inputted. The switch SW₂₁ is disposedbetween the one end of the second capacitive element C₂ and the groundpotential, serving as second discharge means for discharging the chargesaccumulated in the second capacitive element C₂.

The second comparator portion 11 ₂ inputs, at its inverting inputterminal, a voltage V₂ at the one end of the second capacitive elementC₂, and also inputs, at its non-inverting input terminal, the referencevoltage V_(ref) outputted from the reference voltage source 15, tocompare amplitudes between the voltage V₂ and the reference voltageV_(ref), and then outputs a second comparison signal S₂ indicating theresult of the comparison from the output terminal. The second comparisonsignal S₂ is at a high level when the voltage V₂ is less than thereference voltage V_(ref), while being at a low level when the voltageV₂ is greater than the reference voltage V_(ref).

The reference voltage source 15 generates a constant reference voltageV_(ref), which is supplied to the respective non-inverting inputterminals of the first comparator portion 11 ₁ and the second comparatorportion 11 ₂. The SR-type flip-flop circuit 16 inputs, at the S inputterminal, the first comparison signal S₁ outputted from the firstcomparator portion 11 ₁, and also inputs, at the R input terminal, thesecond comparison signal S₂ outputted from the second comparator portion11 ₂, and then outputs output signals, which change as the respectivelevels of the first comparison signal S₁ and the second comparisonsignal S₂ vary, from the Q output terminal and the QB output terminal,respectively. The buffer amplifier 18 amplifies the signal outputtedfrom the Q output terminal of the SR-type flip-flop circuit 16 foroutput to the counter portion 19. The counter portion 19 counts thenumber of pulses per unit time in the signal outputted from the bufferamplifier 18 to output the count as a digital value.

The SR-type flip-flop circuit 16 serves also as timing control means forcontrolling the operation of each switch in accordance with the firstcomparison signal S₁ and the second comparison signal S₂. That is, eachof the switch SW₁ and the switch SW₂₁ is closed when the value of thesignal outputted from the QB output terminal of the SR-type flip-flopcircuit 16 is at the high level, whereas being opened at the low level.On the other hand, each of the switch SW₂ and the switch SW₁₁ is closedwhen the value of the signal outputted from the Q output terminal of theSR-type flip-flop circuit 16 is at the high level, whereas being openedat the low level.

A description will now be made for the operation of the I/F converter 10and the photodetector 1 according to the first embodiment. FIG. 2 is anexplanatory timing chart illustrating the operation of the I/F converter10 according to the first embodiment.

The current outputted from the photodiode PD for which light has beenmade incident is inputted to the input end 10 a of the I/F converter 10and amplified by the current mirror circuit 14, being outputted from thecurrent mirror circuit 14 to the switches SW₁ and SW₂.

Before time t₁, the Q output of the SR-type flip-flop circuit 16 is atthe low level with the QB output at the high level, such that each ofthe switches SW₁ and SW₂₁ is closed while each of the switches SW₂ andSW₁₁ is opened. The current outputted from the current mirror circuit 14flows into the first capacitive element C₁ through the switch SW₁,allowing the charges to be accumulated in the first capacitive elementC₁. As the amount of charges accumulated in the first capacitive elementC₁ increases, the voltage V₁ inputted to the inverting input terminal ofthe first comparator portion 11 ₁ gradually increases and then growsgreater than the reference voltage V_(ref) applied to the non-invertinginput terminal at time t₁. At time t₁, the first comparison signal S₁outputted from the output terminal of the first comparator portion 11 ₁changes from a high level to a low level.

The first comparison signal S₁ thus changes to the low level at time t₁,and this will cause the Q output of the SR-type flip-flop circuit 16 tochange into the high level and the QB output to change to the low level.This causes each of the switches SW₁ and SW₂₁ to be opened, and each ofthe switches SW₂ and SW₁₁ to be closed. The opening and closingoperations of each switch allow the charges accumulated in the firstcapacitive element C₁ to be discharged, and the first comparison signalS₁ outputted from the output terminal of the first comparator portion 11₁ to return to the high level.

After time t₁, the current outputted from the current mirror circuit 14flows into the second capacitive element C₂ through the switch SW₂,allowing the charges to be built up in the second capacitive element C₂.As the amount of charges accumulated in the second capacitive element C₂increases, the voltage V₂ inputted to the inverting input terminal ofthe second comparator portion 11 ₂ gradually increases and then growsgreater than the reference voltage V_(ref) applied to the non-invertinginput terminal at time t₂. At time t₂, the second comparison signal S₂outputted from the output terminal of the second comparator portion 11 ₂changes from a high level to a low level.

The second comparison signal S₂ thus changes to the low level at timet₂, and this will cause the Q output of the SR-type flip-flop circuit 16to change into the low level and the QB output to change to the highlevel. This causes each of the switches SW₁ and SW₂₁ to be closed, andeach of the switches SW₂ and SW₁₁ to be opened. The opening and closingoperations of each switch allow the charges accumulated in the secondcapacitive element C₂ to be discharged, and the second comparison signalS₂ outputted from the output terminal of the second comparator portion11 ₂ to return to the high level.

The operation is repeated in this manner, thereby causing the Q outputsignal of the SR-type flip-flop circuit 16 to form a pulsed signal,which is inputted to the counter portion 19 via the buffer amplifier 18.Then, the counter portion 19 counts the number of pulses per unit timein the signal outputted from the Q output terminal of the SR-typeflip-flop circuit 16, and the value of counts (i.e., the frequency) isoutputted as a digital value. The higher the rate of building up chargesin each of the first capacitive element C₁ and the second capacitiveelement C₂, i.e., the larger the current outputted from the currentmirror circuit 14, the higher the frequency obtained in this manner.

FIG. 3 is a graph showing the operational characteristic of the I/Fconverter 10 and the photodetector 1 according to the first embodiment.In this graph, the horizontal axis represents the intensity of lightmade incident upon the photodiode PD of the photodetector 1 or the valueof current inputted to the input end 10 a of the I/F converter 10. Thevertical axis represents the frequency measured by the counter portion19.

This figure also shows the operational characteristic of the I/Fconverter configured as shown in FIG. 12, as a comparative example, forcomparison to that of the first embodiment. As illustrated in thisfigure, the comparative example shows that the input/output relatedlinearity is degraded in a region where a larger amount of light is madeincident upon the photodiode PD (i.e., in a region with a larger currentvalue). In contrast to this, this embodiment exhibits a goodinput/output related linearity even in the region where a larger amountof light is made incident upon the photodiode PD (i.e., in a region witha larger current value). As such, the I/F converter 10 and thephotodetector 1 according to this embodiment can realize a highinput/output related linearity with high accuracy over a wide dynamicrange.

Second Embodiment

Now, a description will be made for an I/F converter and a photodetectoraccording to a second embodiment of the present invention. FIG. 4 is aview illustrating the configuration of an I/F converter 20 and aphotodetector 2 according to the second embodiment. The photodetector 2illustrated in this figure includes a photodiode PD for outputting acurrent of an amplitude corresponding to the intensity of light madeincident thereon, the I/F converter 20 for inputting a current outputtedfrom the photodiode PD to generate a signal, and a counter portion 29for counting the number of pulses per unit time in the signal generatedby the I/F converter 20.

The I/F converter 20 includes a first comparator portion 21 ₁, a secondcomparator portion 21 ₂, a first overvoltage protection circuit 22 ₁, asecond overvoltage protection circuit 22 ₂, a first one-shot circuit 23₁, a second one-shot circuit 23 ₂, a current mirror circuit 24, areference voltage source 25, an SR-type flip-flop circuit 26, a timingcontrol portion 27, a buffer amplifier 28, a first capacitive elementC₁, a second capacitive element C₂, a third capacitive element C₃, afourth capacitive element C₄, a switch SW₁, a switch SW₂, switches SW₁₁to SW₁₃, switches SW₂₁ to SW₂₃, switches SW₃₁ to SW₃₃, and switches SW₄₁to SW₄₃.

The respective operational characteristics of the first comparatorportion 21 ₁ and the second comparator portion 21 ₂ are identical toeach other. The respective capacitance values of the four capacitiveelements C₁ to C₄ are equal to each other. The I/F converter 20 isconnected at its input end 20 a to the photodiode PD, such that acurrent generated in the photodiode PD is inputted to the input end 20a, allowing a signal at a frequency corresponding to the amplitude ofthe inputted current to be outputted from the buffer amplifier 28 to thecounter portion 29.

The current mirror circuit 24 amplifies the current inputted at theinput end 20 a for output to the switch SW₁ and the switch SW₂. Theswitch SW₁ is disposed between the output end of the current mirrorcircuit 24 and the inverting input terminal of the first comparatorportion 21 ₁. The switch SW₂ is disposed between the output end of thecurrent mirror circuit 24 and the inverting input terminal of the secondcomparator portion 21 ₂. The switch SW₁ and the switch SW₂ serve asswitching means for selectively switching to either one of a firstoutput end (a connection point to the inverting input terminal of thefirst comparator portion 21 ₁) and a second output end (a connectionpoint to the inverting input terminal of the second comparator portion21 ₂) to output the current inputted to the input end 20 a and havingpassed through the current mirror circuit 24.

Each of the first capacitive element C₁ and the third capacitive elementC₃ is connected at one end to the output end of the current mirrorcircuit 24 via the switch SW₁ as well as to the inverting input terminalof the first comparator portion 21 ₁. Each of the first capacitiveelement C₁ and the third capacitive element C₃ can accumulate chargescorresponding to the current inputted.

The switch SW₁₁ is disposed between the one end and the other end of thefirst capacitive element C₁, serving as first discharge means fordischarging the charges accumulated in the first capacitive element C₁.The switch SW₁₂ is disposed between the other end of the firstcapacitive element C₁ and the ground potential. The switch SW₁₃ isdisposed between the other end of the first capacitive element C₁ andthe output terminal of the first comparator portion 21 ₁. The switchesSW₁₂ and SW₁₃ serve as first connection means for selectively setting toeither one of the states with the other end of the first capacitiveelement C₁ connected to the ground potential, with the other end of thefirst capacitive element C₁ connected to the output terminal of thefirst comparator portion 21 ₁, and with the other end of the firstcapacitive element C₁ opened.

The switch SW₃₁ is disposed between the one end and the other end of thethird capacitive element C₃, serving as third discharge means fordischarging the charges accumulated in the third capacitive element C₃.The switch SW₃₂ is disposed between the other end of the thirdcapacitive element C₃ and the ground potential. The switch SW₃₃ isdisposed between the other end of the third capacitive element C₃ andthe output terminal of the first comparator portion 21 ₁. The switchesSW₃₂ and SW₃₃ serve as third connection means for selectively setting toeither one of the states with the other end of the third capacitiveelement C₃ connected to the ground potential, with the other end of thethird capacitive element C₃ connected to the output terminal of thefirst comparator portion 21 ₁, and with the other end of the thirdcapacitive element C₃ opened.

The first comparator portion 21 ₁ inputs, at its inverting inputterminal, a voltage V₁ at the one end of each of the first capacitiveelement C₁ and the third capacitive element C₃, and also inputs, at itsnon-inverting input terminal, a reference voltage V_(ref) outputted fromthe reference voltage source 25, to compare amplitudes between thevoltage V₁ and the reference voltage V_(ref), and then outputs a firstcomparison signal S₁ indicating the result of the comparison from theoutput terminal. The first comparison signal S₁ is at the high levelwhen the voltage V₁ is less than the reference voltage V_(ref), whilebeing at the low level when the voltage V₁ is greater than the referencevoltage V_(ref).

Each of the second capacitive element C₂ and the fourth capacitiveelement C₄ is connected at one end to the output end of the currentmirror circuit 24 via the switch SW₂ as well as to the inverting inputterminal of the second comparator portion 21 ₂. Each of the secondcapacitive element C₂ and the fourth capacitive element C₄ canaccumulate charges corresponding to the current inputted.

The switch SW₂₁ is disposed between the one end and the other end of thesecond capacitive element C₂, serving as second discharge means fordischarging the charges accumulated in the second capacitive element C₂.The switch SW₂₂ is disposed between the other end of the secondcapacitive element C₂ and the ground potential. The switch SW₂₃ isdisposed between the other end of the second capacitive element C₂ andthe output terminal of the second comparator portion 21 ₂. The switchesSW₂₂ and SW₂₃ serve as second connection means for selectively settingto either one of the states with the other end of the second capacitiveelement C₂ connected to the ground potential, with the other end of thesecond capacitive element C₂ connected to the output terminal of thesecond comparator portion 21 ₂, and with the other end of the secondcapacitive element C₂ opened.

The switch SW₄₁ is disposed between the one end and the other end of thefourth capacitive element C₄, serving as fourth discharge means fordischarging the charges accumulated in the fourth capacitive element C₄.The switch SW₄₂ is disposed between the other end of the fourthcapacitive element C₄ and the ground potential. The switch SW₄₃ isdisposed between the other end of the fourth capacitive element C₄ andthe output terminal of the second comparator portion 21 ₂. The switchesSW₄₂ and SW₄₃ serve as fourth connection means for selectively settingto either one of the states with the other end of the fourth capacitiveelement C₄ connected to the ground potential, with the other end of thefourth capacitive element C₄ connected to the output terminal of thesecond comparator portion 21 ₂, and with the other end of the fourthcapacitive element C₄ opened.

The second comparator portion 21 ₂ inputs, at its inverting inputterminal, a voltage V₂ at the one end of each of the second capacitiveelement C₂ and the fourth capacitive element C₄, and also inputs, at itsnon-inverting input terminal, a reference voltage V_(ref) outputted fromthe reference voltage source 25, to compare amplitudes between thevoltage V₂ and the reference voltage V_(ref), and then outputs a secondcomparison signal S₂ indicating the result of the comparison from theoutput terminal. The second comparison signal S₂ is at the high levelwhen the voltage V₂ is less than the reference voltage V_(ref), whilebeing at the low level when the voltage V₂ is greater than the referencevoltage V_(ref).

The first overvoltage protection circuit 22 ₁ is connected to theinverting input terminal of the first comparator portion 21 ₁ to resetthe potential at the inverting input terminal. Likewise, the secondovervoltage protection circuit 22 ₂ is connected to the inverting inputterminal of the second comparator portion 21 ₂ to reset the potential atthe inverting input terminal. Each of the first comparator portion 21 ₁and the second comparator portion 21 ₂ would not properly operate in asteady state with the voltage at the inverting input terminal beinghigher than that at the non-inverting input terminal. Such a situationlikely occurs when the power is actuated. In this context, the firstovervoltage protection circuit 22 ₁ and the second overvoltageprotection circuit 22 ₂ will reset the potential at the respectiveinverting input terminals of the first comparator portion 21 ₁ and thesecond comparator portion 21 ₂, thereby enabling a proper operation.

The first one-shot circuit 23 ₁ is disposed between the output terminalof the first comparator portion 21 ₁ and the S input terminal of theSR-type flip-flop circuit 26 so as to stabilize changes in level of thefirst comparison signal S₁ outputted from the first comparator portion21 ₁. The second one-shot circuit 23 ₂ is disposed between the outputterminal of the second comparator portion 21 ₂ and the R input terminalof the SR-type flip-flop circuit 26 so as to stabilize changes in levelof the second comparison signal S₂ outputted from the second comparatorportion 21 ₂. Each of the first one-shot circuit 23 ₁ and the secondone-shot circuit 23 ₂ stabilizes the operation of the SR-type flip-flopcircuit 26.

The reference voltage source 25 generates a constant reference voltageV_(ref), which is inputted to the respective non-inverting inputterminals of the first comparator portion 21 ₁ and the second comparatorportion 21 ₂. The SR-type flip-flop circuit 26 inputs, at the S inputterminal, the first comparison signal S₁ outputted from the firstcomparator portion 21 ₁ and having passed through the first one-shotcircuit 23 ₁, and also inputs, at the R input terminal, the secondcomparison signal S₂ outputted from the second comparator portion 21 ₂and having passed through the second one-shot circuit 23 ₂, and thenoutputs output signals, which change as the respective levels of thefirst comparison signal S₁ and the second comparison signal S₂ vary,from the Q output terminal and the QB output terminal, respectively. Thebuffer amplifier 28 amplifies the signal outputted from the Q outputterminal of the SR-type flip-flop circuit 26 for output to the counterportion 29. The counter portion 29 counts the number of pulses per unittime in the signal outputted from the buffer amplifier 28 to output thecount as a digital value.

The SR-type flip-flop circuit 26 and the timing control portion 27 serveas timing control means for controlling the operation of each switch inaccordance with the first comparison signal S₁ and the second comparisonsignal S₂. That is, the timing control portion 27 generates and outputsa control signal to control the operation of each switch in accordancewith the respective output signals from the Q output terminal and the QBoutput terminal of the SR-type flip-flop circuit 26. Then, each switchis closed when the value of the control signal outputted and providedfrom the timing control portion 27 is at the high level, whereas beingopened at the low level.

FIG. 5 is a view illustrating an exemplary circuit of each of the firstcomparator portion 21 ₁ and the second comparator portion 21 ₂. Acomparator portion 21 illustrated in this figure is representative ofthe first comparator portion 21 ₁ and the second comparator portion 21₂. The comparator portion 21 includes p-channel CMOS transistors T₁₁ toT₁₅, n-channel CMOS transistors T₂₁ to T₂₅, a phase compensationcapacitive element C, and a resistive element R, which are connected asillustrated.

The inverting input terminal P_(M), which is connected to the gateterminal of the transistor T₁₄, inputs the voltage V₁ or V₂. Thenon-inverting input terminal P_(P), which is connected to the gateterminal of the transistor T₁₅, inputs the reference voltage V_(ref).The output terminal P_(O), which is connected to the drain terminal ofeach of the transistors T₁₃, T₂₁, and T₂₄, outputs the first comparisonsignal S₁ or the second comparison signal S₂. The bias input terminalP_(B), which is connected to the gate terminal of each of thetransistors T₁₁ to T₁₃, sets the bias voltage for operating thecomparator portion 21. The control terminal P_(C), which is connected tothe gate terminal of each of the transistors T₂₁ and T₂₅, switchesbetween the modes of operation of the comparator portion 21 (i.e., thecomparator mode and the amplifier mode) by connecting or disconnectingthe phase compensation capacitive element C. The supply terminal V_(dd)is for inputting a supply voltage.

FIG. 6 is a view illustrating an exemplary circuit of each of the firstovervoltage protection circuit 22 ₁ and the second overvoltageprotection circuit 22 ₂. An overvoltage protection circuit 22illustrated in this figure is representative of the first overvoltageprotection circuit 22 ₁ and the second overvoltage protection circuit 22₂. The overvoltage protection circuit 22 includes p-channel CMOStransistors T₃₁ to T₃₆, n-channel CMOS transistors T₄₁ to T₅₀, andSchmitt triggers U₁ and U₂, which are connected as illustrated.

The bias input terminal P_(B), which is connected to the gate terminalof each of the transistors T₃₁ to T₃₃ and the drain terminal of thetransistor T₃₁, sets the bias voltage for operating the overvoltageprotection circuit 22. The terminal P_(O), which is connected to thegate terminal of the transistor T₄₃ and the drain terminal of thetransistor T₅₀, is connected to the output terminal of the firstcomparator portion 21 ₁ and the second comparator portion 21 ₂.

The bias input terminal P_(B) biases the circuit. The terminal P_(O)serves as an input and output terminal. When having reached a presetvoltage or no less than the preset voltage, the terminal P_(O) isinstantaneously forced to the ground potential due to the transistorT₅₀. When the terminal P_(O) is at the ground potential (or no greaterthan the ground potential), the circuit of FIG. 6 is stabilized. Thestabilized terminal P_(O) is in a high-impedance state, having noeffects on the circuit to which the terminal P_(O) is connected. Thesupply terminal V_(dd) is for inputting a supply voltage.

A description will now be made to the operation of the I/F converter 20and the photodetector 2 according to the second embodiment. FIG. 7 is anexplanatory timing chart illustrating the operation of the I/F converter20 according to the second embodiment. In this figure, φ₁ denotes acontrol signal which controls the opening and closing operation of theswitch SW₁, φ_(ij) denotes a control signal which controls the openingand closing operation of the switch SW_(ij) (i=1 to 4, j=1 to 3), φ_(C1)denotes a control signal which is inputted to the control terminal P_(C)of the first comparator portion 21 ₁ to switch between the modes ofoperation of the first comparator portion 21 ₁, and φ_(C2) denotes acontrol signal which is inputted to the control terminal P_(C) of thesecond comparator portion 21 ₂ to switch between the modes of operationof the second comparator portion 21 ₂. Although not illustrated, acontrol signal φ₂ for controlling the opening and closing operation ofthe switch SW₂ is a level inverted signal of the control signal φ₁.

These control signals φ₁, φ₂, φ_(ij), φ_(C1), and φ_(C2) are outputtedfrom the timing control portion 27. FIGS. 8A to 10C are explanatoryviews illustrating how each switch is opened or closed at each point intime and how each capacitive element is connected during operation ofthe I/F converter 20 according to the second embodiment.

The current outputted from the photodiode PD for which light has beenmade incident is inputted to the input end 20 a of the I/F converter 20and amplified by the current mirror circuit 24, being outputted from thecurrent mirror circuit 24 to the switches SW₁ and SW₂.

FIG. 8A shows how each switch is opened or closed and how eachcapacitive element is connected at time t₀. At time t₀, the Q output ofthe SR-type flip-flop circuit 26 is at the low level with the QB outputat the high level. Additionally, the control signal φ₁ is at the lowlevel, the switch SW₁ is opened, the control signal φ₂ is at the highlevel, and the switch SW₂ is closed. As a result, the current outputtedfrom the current mirror circuit 24 will not flow toward the firstcomparator portion 21 ₁ but will flow toward the second comparatorportion 21 ₂.

At time t₀, the control signal φ₁₁ is at the low level, the switch SW₁,is opened, the control signal φ₁₂ is at the low level, the switch SW₁₂is opened, the control signal φ₁₃ is at the high level, and the switchSW₁₃ is closed. As a result, the first capacitive element C₁ isconnected as a feedback capacitive element between the inverting inputterminal and the output terminal of the first comparator portion 21 ₁.The control signal φ₃₁ is at the low level, the switch SW₃₁ is opened,the control signal φ₃₂ is at the high level, the switch SW₃₂ is closed,the control signal φ₃₃ is at the low level, and the switch SW₃₃ isopened. As a result, the third capacitive element C₃ is connectedbetween the inverting input terminal of the first comparator portion 21₁ and the ground potential to be charged at the reference voltageV_(ref). The control signal φ_(C1) is at the high level and the firstcomparator portion 21 ₁ is in the amplifier mode. The first comparisonsignal S₁ outputted from the output terminal of the first comparatorportion 21 ₁ is at the low level.

At time t₀, the control signal φ₂₁ is at the high level, the switch SW₂,is closed, the control signal φ₂₂ is at the low level, the switch SW₂₂is opened, the control signal φ₂₃ is at the low level, and the switchSW₂₃ is opened. As a result, the second capacitive element C₂ isshort-circuited at the ends being disconnected from the output terminalof the second comparator portion 21 ₂. The control signal φ₄₁ is at thelow level, the switch SW₄₁ is opened, the control signal φ₄₂ is at thehigh level, the switch SW₄₂ is closed, the control signal φ₄₃ is at thelow level, and the switch SW₄₃ is opened. As a result, the fourthcapacitive element C₄ is connected between the inverting input terminalof the second comparator portion 21 ₂ and the ground potential, andaccumulates the charges corresponding to the current having flowntherein. Here, the voltage at the inverting input terminal of the secondcomparator portion 21 ₂ is below the reference voltage V_(ref). Thecontrol signal φ_(C2) is at the low level and the second comparatorportion 21 ₂ is in the comparator mode. The second comparison signal S₂outputted from the output terminal of the second comparator portion 21 ₂is at the high level.

After time t₀, the current outputted from the current mirror circuit 24and then flowing toward the second comparator portion 21 ₂ side causesthe amount of charges accumulated in the fourth capacitive element C₄ togradually increase, thereby allowing the voltage at the inverting inputterminal of the second comparator portion 21 ₂ to gradually increase aswell. Then, at time t₁, the voltage at the inverting input terminal ofthe second comparator portion 21 ₂ reaches the reference voltageV_(ref), and the second comparison signal S₂ outputted from the outputterminal of the second comparator portion 21 ₂ changes to the low level,the Q output of the SR-type flip-flop circuit 26 to the high level, andthe QB output to the low level.

FIG. 8B shows how each switch is opened or closed and how eachcapacitive element is connected after time t₁. At time t₁, the controlsignal φ₁₃ changes into the low level and the switch SW₁₃ is opened, andsubsequently, the first capacitive element C₁ retains the charges thathave been accumulated. The control signal φ₂₁ changes into the low leveland the switch SW₂₁ is opened, and subsequently, the second capacitiveelement C₂ is released from the state with the ends short-circuited. Thecontrol signal φ_(C2) changes into the high level and the secondcomparator portion 21 ₂ is turned into the amplifier mode.

FIG. 8C shows how each switch is opened or closed and how eachcapacitive element is connected after time t₂ at which a certain timehas elapsed from time t₁. At time t₂, the control signal φ₃₁ changesinto the high level and the switch SW₃₁ is closed, and subsequently, thethird capacitive element C₃ is short-circuited at the ends to bedischarged. The control signal φ_(C1) changes into the low level and thefirst comparator portion 21 ₁ is turned to the comparator mode. Thefirst comparison signal S₁ outputted from the output terminal of thefirst comparator portion 21 ₁ changes into the high level.

FIG. 9A shows how each switch is opened or closed and how eachcapacitive element is connected after time t₃ at which a certain timehas elapsed from time t₂. At time t₃, the control signal φ₃₂ changesinto the low level and the switch SW₃₂ is opened, and subsequently, thethird capacitive element C₃ is disconnected, with the ends thereofremaining short-circuited, from the output terminal of the firstcomparator portion 21 ₁.

FIG. 9B shows how each switch is opened or closed and how eachcapacitive element is connected after time t₄ at which a certain timehas elapsed from time t₃. At time t₄, the control signal φ₁₂ changesinto the high level and the switch SW₁₂ is closed, and subsequently, thefirst capacitive element C₁ is connected between the inverting inputterminal of the first comparator portion 21 ₁ and the ground potential.Additionally, the voltage at the inverting input terminal of the firstcomparator portion 21 ₁ takes a value corresponding to the amount ofcharges retained in the first capacitive element C₁ at time t₁.

FIG. 9C shows how each switch is opened or closed and how eachcapacitive element is connected after time t₅ at which a certain timehas elapsed from time 4. At time t₅, the control signal φ₁ changes intothe high level and the switch SW₁ is closed, and the control signal φ₂changes into the low level and the switch SW₂ is opened, therebystopping the accumulation of charges in the fourth capacitive element C₄that has been carried out until then. After time t₅, the voltage at theinverting input terminal of the second comparator portion 21 ₂ is abovethe reference voltage V_(ref). In addition, after time t₅, the currentoutputted from the current mirror circuit 24 flows into the firstcomparator portion 21 ₁ side, thereby causing the first capacitiveelement C₁ to accumulate the charges therein corresponding to the flowedin current.

FIG. 10A shows how each switch is opened or closed and how eachcapacitive element is connected after time t₆ at which a certain timehas elapsed from time t₅. At time t₆, the control signal φ₂₃ changesinto the high level and the switch SW₂₃ is closed, and subsequently, thesecond capacitive element C₂ is connected between the inverting inputterminal and the output terminal of the second comparator portion 21 ₂.Additionally, after time t₆, the voltage at the inverting input terminalof the second comparator portion 21 ₂ takes the reference voltageV_(ref). The charge (hereinafter referred to as the excess charge)exceeding the charge corresponding to the reference voltage V_(ref) inthe charge which have been accumulated in the fourth capacitive elementC₄ before time t₆ moves to the second capacitive element C₂ serving asthe feedback capacitive element. The movement of the charge requirestime corresponding to the response speed of the second comparatorportion 21 ₂.

After time t₆, the current outputted from the current mirror circuit 24and then flowing toward the first comparator portion 21 ₁ side causesthe amount of charges accumulated in the first capacitive element C₁ togradually increase, thereby allowing the voltage at the inverting inputterminal of the first comparator portion 21 ₁ to gradually increase aswell. Then, at time t₇, the voltage at the inverting input terminal ofthe first comparison signal S₁ reaches the reference voltage V_(ref),and the first comparison signal S₁ outputted from the output terminal ofthe first comparator portion 21 ₁ changes to the low level, the Q outputof the SR-type flip-flop circuit 26 to the low level, and the QB outputto the high level.

FIG. 10B shows how each switch is opened or closed and how eachcapacitive element is connected after time t₇. At time t₇, the controlsignal φ₃₁ changes into the low level and the switch SW₃₁ is opened, andsubsequently, the third capacitive element C₃ is released from the statewith the ends short-circuited. The control signal φ₂₃ changes into thelow level and the switch SW₂₃ is opened, and subsequently, the secondcapacitive element C₂ retains the charges that have been accumulated.The control signal φ_(C1) changes into the high level and the firstcomparator portion 21 ₁ is turned into the amplifier mode.

FIG. 10C shows how each switch is opened or closed and how eachcapacitive element is connected after time t₈ at which a certain timehas elapsed from time t₇. At time t₈, the control signal φ₄₁ changesinto the high level and the switch SW₄, is closed, and subsequently, thefourth capacitive element C₄ is short-circuited at the ends to bedischarged. The control signal φ_(C2) changes into the low level and thesecond comparator portion 21 ₂ is turned to the comparator mode. Thesecond comparison signal S₂ outputted from the output terminal of thesecond comparator portion 21 ₂ changes into the high level.

Thereafter, the operation is carried out in the same manner. Here,charges are accumulated in the fourth capacitive element C₄ from time t₀to time t₅. Thereafter, charges are accumulated in the first capacitiveelement C₁, the second capacitive element C₂, the third capacitiveelement C₃, and the fourth capacitive element C₄ repeatedly in thatorder. The operations repeated as described above cause the SR-typeflip-flop circuit 26 to form a pulsed Q output signal, which is inputtedto the counter portion 29 through the buffer amplifier 28. Then, thecounter portion 29 counts the number of pulses per unit time in thesignal outputted from the Q output terminal of the SR-type flip-flopcircuit 26, and the value of counts (i.e., the frequency) is outputtedas a digital value. The higher the rate of building up charges in eachcapacitive element, i.e., the larger the current outputted from thecurrent mirror circuit 24, the higher the frequency obtained in thismanner.

For example, when the charge accumulation is switched from the fourthcapacitive element C₄ to the first capacitive element C₁, the excesscharge in the charges that have been accumulated in the fourthcapacitive element C₄ moves to the second capacitive element C₂. Then,after the charge accumulation is switched from the first capacitiveelement C₁ to the second capacitive element C₂, charges are additionallybuilt up in the second capacitive element C₂ in addition to the excesscharge that has been accumulated therein. In this manner, when thecapacitive elements are switched therebetween to build up charges, theexcess charge is not discarded but moved to and built up in the othercapacitive element. Accordingly, the I/F converter 20 and thephotodetector 2 according to this embodiment can realize a highinput/output related linearity with high accuracy over a wide dynamicrange.

FIGS. 11A and 11B are views illustrating the operational characteristicsof the I/F converter 10 of the first embodiment and those of the I/Fconverter 20 of the second embodiment for comparison purposes. FIG. 11Ais a graph showing the relationship between the input current value andthe output frequency, FIG. 11B being a graph showing the relationshipbetween the input current value and the linearity. The linearity isindicated with the amount of change in output frequency assumed to oneover the range of the input current values from 1 nA to 10 nA. Asillustrated in this figure, in either of the first and secondembodiments, a high input/output related linearity is realized with highaccuracy over a wide dynamic range. When compared with the firstembodiment, the second embodiment has realized a high input/outputrelated linearity with high accuracy over a wider dynamic range.

INDUSTRIAL APPLICABILITY

As described above in detail, the I/F converter and the photodetectoraccording to the present invention is available as one which can realizea high input/output related linearity with high accuracy over a widedynamic range.

1. An I/F converter for generating a signal at a frequency correspondingto an amplitude of a current inputted to an input end, the I/F convertercomprising switching means for selectively switching to either one of afirst output end and a second output end to output the current inputtedto the input end, a first capacitive element connected to the firstoutput end of the switching means to accumulate charge corresponding toinputted current, first discharge means for discharging the chargeaccumulated in the first capacitive element, a first comparator portionconnected at its input terminal to one end of the first capacitiveelement to compare amplitudes between a voltage at the one end of thefirst capacitive element and a reference voltage, the first comparatorportion outputting from its output terminal a first comparison signalindicating a result of the comparison, a second capacitive elementconnected to the second output end of the switching means to accumulatecharge corresponding to inputted current, second discharge means fordischarging the charge accumulated in the second capacitive element, anda second comparator portion connected at its input terminal to one endof the second capacitive element to compare amplitudes between a voltageat the one end of the second capacitive element and a reference voltage,the second comparator portion outputting from its output terminal asecond comparison signal indicating a result of the comparison, whereinwhen the switching means is set so that the switching means allows thecurrent to be outputted to the first output end, the current inputted atthe input end flows into the first capacitive element via the switchingmeans, and when the switching means is set so that the switching meansallows the current to be outputted to the second output end, the currentinputted at the input end flows into the second capacitive element viathe switching means.
 2. The I/F converter according to claim 1, furthercomprising timing control means for controlling an operation of each ofthe switching means, the first discharge means, and the second dischargemeans in accordance with the first comparison signal and the secondcomparison signal.
 3. The I/F converter according to claim 1, furthercomprising a reference voltage source for supplying the referencevoltage to each of the first comparator portion and the secondcomparator portion.
 4. The I/F converter according to claim 1, furthercomprising a current mirror circuit for amplifying a current inputted tothe input end for output to the switching means.
 5. The I/F converteraccording to claim 1, wherein the switching means includes a firstswitch disposed between the input end and the first output end, and asecond switch disposed between the input end and the second output end.6. The I/F converter according to claim 1, further comprising outputmeans for inputting the first comparison signal and the secondcomparison signal, and outputting an output signal, which changes inresponse to variations in the respective levels of the first comparisonsignal and the second comparison signal.
 7. The I/F converter accordingto claim 6, wherein the output means is an SR-type flip-flop circuit. 8.An I/F converter for generating a signal at a frequency corresponding toan amplitude of a current inputted to an input end, the I/F convertercomprising switching means for selectively switching to either one of afirst output end and a second output end to output the current inputtedto the input end, a first capacitive element connected to the firstoutput end of the switching means to accumulate charge corresponding toinputted current, first discharge means for discharging the chargeaccumulated in the first capacitive element, a first comparator portionconnected at its input terminal to one end of the first capacitiveelement to compare amplitudes between a voltage at the one end of thefirst capacitive element and a reference voltage, the first comparatorportion outputting from its output terminal a first comparison signalindicating a result of the comparison, a second capacitive elementconnected to the second output end of the switching means to accumulatecharge corresponding to inputted current, second discharge means fordischarging the charge accumulated in the second capacitive element, asecond comparator portion connected at its input terminal to one end ofthe second capacitive element to compare amplitudes between a voltage atthe one end of the second capacitive element and a reference voltage,the second comparator portion outputting from its output terminal asecond comparison signal indicating a result of the comparison, and anSR-type flip-flop circuit for inputting the first comparison signal andthe second comparison signal.
 9. A photodetector, comprising aphotosensitive element for outputting a current corresponding inamplitude to an intensity of light made incident, and an I/F converteraccording to claim 1 for inputting a current outputted from thephotosensitive element to generate a signal at a frequency correspondingto an amplitude of the current.
 10. The photodetector according to claim9, further comprising a counter portion for counting the number ofpulses per unit time in the signal generated in the I/F converter.